Digital electronics represent signals by discrete bands of analog levels. All levels within a band represent the same signal state. The number of these states is two in general, and they are represented by two voltage bands: one near a reference value (typically termed as “ground” or zero volts) and a value near the supply voltage, corresponding to the “false” (“0”) and “true” (“1”) values of the Boolean domain respectively.
According to the state of the art, for providing a supply voltage first supply potential terminal (VDD) and second supply potential terminal (VSS) are used. In most cases, VDD is 5V or 3.3V and VSS is 0V, resulting in VDD representing “true” and VSS representing “false”. In the alternative, VDD may for example be 2.5V, 1.8V or other common voltage values.
In digital logic, an inverter or NOT gate is a logic gate which implements logical negation. An inverter circuit outputs a voltage representing the opposite logic-level to its input.
Such inverters can be constructed using a single NMOS transistor or a single PMOS transistor coupled with a resistor or using two complementary transistors in a CMOS configuration. A CMOS input should always be connected to VDD or VSS according to the state of the art. Because the input impedance of a CMOS is very high, the output will be unstable if the input is left open. Moreover, it may lead to increased consumption current due to the through current or malfunction. Therefore, in most cases so called pull-up or pull-down resistors are used to provide a “true” at the valid input of an inverter in case of an open input is applied.
The truth table of inverters according to the state of the art is therefore that a “true” at the input of the inverter results in a “false” at the output of the inverter, a “false” at the input of the inverter results in a “true” at the output of the inverter. An open input results in a “true” at the input of the inverter if a pull-up resistor is used and in a “false” at the output of the inverter.
One disadvantage of the detecting input signals is therefore, that only to two levels corresponding to “true” and “false” can be detected, while open inputs have to be avoided.
It is therefore one objective of the present disclosure to provide an apparatus and a method for improving the detection of inputs. Moreover, it is one objective of the present disclosure to provide an apparatus and a method for three-level input detection.